Staff Engineer - Physical Design at Ambiq Micro, Inc.

Singapore, , Singapore -

Full Time

Start Date

Immediate

Expiry Date

08 Sep, 26

Salary

0.0

Posted On

10 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, Floorplanning, Placement, Clock Tree Synthesis, Routing, Physical Verification, DFM, Timing Closure, IR Drop Analysis, EM Closure, Signal Integrity, Cadence Innovus, Synopsys Fusion Compiler, TCL Scripting, Python, FinFET

Industry

Semiconductor Manufacturing

Description

Company Overview Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us — the intelligence everywhere revolution starts here. Scope Ambiq is looking for a Physical Design Staff Engineer to help bring our advanced SoC designs from netlist to GDS. In this role, you will lead top-level physical implementation and help deliver high-quality silicon that meets challenging performance, power, and area targets. You will work closely with cross-functional teams, including Middle End, DFT, Front End, ARC, and Package teams, to build efficient, manufacturable physical layouts for multi-power-domain designs. This role is well suited for someone who is technically strong, collaborative, self-driven, and excited to work on advanced process technologies and low-power semiconductor products. Responsibilities Lead the physical design flow from netlist to GDS, including floorplanning, placement, clock tree synthesis, routing, physical verification, and DFM. Drive timing closure, IR drop and EM closure, signal integrity analysis, and layout violation resolution. Use industry-standard EDA tools from Cadence and Synopsys for place and route, static timing analysis, physical verification, and signoff analysis. Apply strong methodology expertise in placement and routing for FinFET and multi-patterning process technologies. Work closely with designers, synthesis engineers, DFT engineers, and other stakeholders to resolve implementation challenges. Improve physical design methodologies, scripts, and flows to increase efficiency, consistency, and quality. Stay current with advancements in physical design, EDA tools, and new process nodes. Qualifications Master or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. At least 8 years of experience in integrated circuit physical design. Strong experience with physical design flows, including floorplanning, placement, routing, clock tree synthesis, and physical verification. Hands-on experience with Cadence Innovus and/or Synopsys Fusion Compiler. Solid understanding of digital circuit design principles. Experience with timing closure, power integrity, signal integrity, IR drop, and EM analysis. Proficiency with industry-standard EDA tools from Cadence and Synopsys. Strong analytical, problem-solving, and communication skills. Ability to work effectively with cross-functional engineering teams. Experience with TCL scripting; Python experience is a plus. Fluency in English and Mandarin is required, as this role involves close collaboration with Chinese engineering counterparts.

Responsibilities

Lead the physical design flow from netlist to GDS, focusing on top-level implementation for advanced SoC designs. Drive timing, power, and area closure while collaborating with cross-functional teams to ensure manufacturable layouts.