Staff Engineer, VLSI Design Engineering (RTL Design, UVM validation, and Em at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

09 Mar, 26

Salary

0.0

Posted On

09 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Verilog, SystemVerilog, UVM, Digital Design, Emulation, Simulation, Debugging, Scripting, SoC Architecture, Interface Protocols, Memory Technologies, Problem Solving, Communication, Testbench Development, Automation, Integration

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are looking for a highly motivated engineer to develop synthesizable RTL models, validate them using UVM testbenches, and deliver optimized emulation-ready designs to our emulation team. This role is critical in enabling pre-silicon validation and accelerating software bring-up for complex SoCs. Key Responsibilities: Develop clean, synthesizable RTL models for IP blocks and subsystems using Verilog/SystemVerilog. Collaborate with design teams to ensure RTL is emulation-friendly and meets performance and debug requirements. Create and maintain UVM-based testbenches to validate RTL functionality and coverage. Debug RTL and testbench issues using simulation and emulation tools. Package and deliver validated RTL models to the emulation team, including synthesis scripts, configuration files, and documentation. Support emulation bring-up and assist in resolving integration issues. Qualifications Qualifications: 4 to 7 years of experience in RTL design, UVM validation, and emulation support. Bachelors/Masters from a reputed College/University with Electronics and communication/Embedded Systems background Strong Problem Solving and Debug skills Efficient Communication Tools/Languages: Verilog, SystemVerilog, UVM Familiar with Xcellium, Palladium Required Skills: Strong expertise in Verilog/SystemVerilog RTL coding and digital design fundamentals. Hands-on experience with UVM methodology and testbench development. Familiarity with emulation platforms (e.g., Cadence Palladium, Protium, Synopsys ZeBu, Mentor Veloce). Proficiency in simulation tools (e.g., VCS, Questa, Xcelium) and waveform debug. Scripting skills in Python, TCL, or Perl for automation and testbench control. Understanding of SoC architecture, clock/reset domains, and interface protocols (AXI, APB, PCIe, etc.). Must have strong hold on Digital Design Concepts Circuits/Logic - Knowledge on Memory would be preferable (SRAM/DRAM/ROM/Flash) Customer Interactions and support required for delivered model Debug failures and root-cause it by interacting with other teams/groups Etc Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Responsibilities

The engineer will develop synthesizable RTL models, validate them using UVM testbenches, and deliver optimized emulation-ready designs. This role is critical for enabling pre-silicon validation and accelerating software bring-up for complex SoCs.