Start Date
Immediate
Expiry Date
18 Jun, 26
Salary
0.0
Posted On
20 Mar, 26
Experience
5 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
Gate Level Simulations, Logic Schematic Analysis, CMOS, Verilog Simulations, SystemVerilog, PLI Coding, UVM Test Bench, DRAM, SRAM, Timings Analysis, Setup/Hold Analysis, AI-Assisted Tools, Debugging, Verification Methodology, Test Benches, Test Vectors
Industry
Semiconductor Manufacturing