Staff / Senior Staff Engineer, Physical Design at Renesas Electronics

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

25 Jun, 26

Salary

0.0

Posted On

27 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, SoC, Timing Closure, Congestion Mitigation, Power Integrity, Clocking Methodologies, RTL Design, STA, Verification, Synopsys ICC2, Fusion Compiler, PrimeTime, Cadence Innovus, Tempus, Tcl, Python

Industry

Semiconductor Manufacturing

Description

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employeess roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications. Renesas India is seeking an experienced Staff / Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies. Key Responsibilities Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure Proactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions Qualifications 8+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs Strong expertise in: Timing closure and constraint management Congestion analysis and resolution Power integrity and power-aware physical implementation Block and subsystem-level physical design flows Solid understanding of SoC-level floorplanning and clocking methodologies, including: Clock domain partitioning Clock tree architecture Skew management Clock gating (Candidate is expected to collaborate effectively at the SoC level, not lead these activities.) Hands-on experience with industry-standard tools such as: Synopsys ICC2, Fusion Compiler, PrimeTime Cadence Innovus, Tempus, Certus Signoff and analysis platforms Proficiency in scripting and automation using Tcl, Python, and/or Perl Deep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams Strong understanding of low-power design techniques and power-aware implementation methodologies Education B.Tech or M.Tech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning. Employment Type: Regular (PERM) Remote Work Available: No

Responsibilities

This role involves leading block- and subsystem-level physical design closure, focusing on timing, congestion, and power integrity for complex hierarchical SoCs at advanced technology nodes. The engineer will also develop and scale subsystem closure methodologies and mentor other engineers within the subsystem teams.