Staff/ Senior Staff NPI Debug Engineer at Altera

San Jose, California, United States -

Full Time

Start Date

Immediate

Expiry Date

15 Aug, 26

Salary

215000.0

Posted On

17 May, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Hardware Debug, NPI Engineering, Yield Analysis, Analog Debug, Mixed-Signal Debug, Fault Tree Analysis, Design of Experiments, Python, JMP, Failure Analysis, Fault Isolation, ATE Test Data Analysis, Signal Integrity, Power Delivery Analysis, Technical Leadership, Cross-functional Orchestration

Industry

technology;Information and Internet

Description

Job Details: Job Description: About Altera At Altera™, our independence as the world’s largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry. About The Role Altera is seeking a Staff / Senior Staff NPI (New Product Introduction) Debug Engineer to serve as a key senior technical leader for our most critical hardware investigations. In this high-impact role, you will take point on complex NPI escalations, leading cross-functional debug taskforces to resolve gating silicon issues across silicon, design, and test domains. You will share taskforce leadership responsibilities with other senior members of the team, acting as the primary orchestrator for investigations that heavily involve analog, mixed-signal, and power delivery challenges. This is a highly technical senior individual contributor role requiring a unique blend of deep hardware debug expertise, yield analysis proficiency, and strong crisis-management skills. You will analyze complex issues firsthand, define fault trees, guide parallel investigations across global engineering teams, and present root-cause findings to executive leadership. Why Altera • Serve as a senior technical leader orchestrating taskforces for cutting-edge FPGA programs. • Act as the go-to expert for complex analog, power, and mixed-signal escalations. • Orchestrate problem-solving across world-class design, validation, product, test, and manufacturing teams. • Gain high executive visibility by driving recovery plans for Altera’s most complex hardware blockers. • Mentor engineers and establish the blueprint for structured debug and root-cause analysis. Key Responsibilities: Taskforce Leadership & Critical Issue Resolution • Drive Debug Taskforces: Act as the technical lead and orchestrator for designated cross-functional "tiger teams" formed to solve critical NPI blockers, especially those involving complex analog, power, or signal integrity interactions. • Define the Debug Strategy: Develop comprehensive fault trees, design of experiments (DOEs), and parallel investigation paths. Assign clear ownership across Design, Product, Test, Validation, and Manufacturing teams. • Synthesize Complex Data: Aggregate and analyze findings from simulation/circuit analysis, ATE test data, failure analysis (FA) and yield signatures to rapidly close in on root cause. • Executive Communication: Lead taskforce syncs, maintain clear dashboards, and present high-level readouts, recovery schedules, and risk assessments to leadership. Yield Analysis & Manufacturing Excellence • Lead complex yield analysis activities directly related to NPI investigations, including yield pareto, parametric shift analysis, tester correlation, and statistical data review. • Identify systemic yield detractors and lead corrective actions across the foundry/fab, assembly, test, and design teams. • Influence test program development, diagnostic coverage, and outlier detection screening to prevent taskforce-level escapes. • Track yield by lot, wafer, and unit to proactively catch issues before they escalate. Deep Hardware Debug • Knowledge of advanced lab equipment, fault isolation and failure analysis tools to identify the best methodologies for debug and interpet the failure analysis data to direct the debug. • Guide experimental builds and validation of engineering fixes proposed by the taskforces. Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $149,100 - $215,000 USD We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations. #MD-1 Qualifications: Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, or related technical field. Master’s or PhD preferred. 6+ years of experience in hardware debug, NPI engineering, product/yield engineering, or system validation 6+ years leading technical taskforces to resolve critical silicon, hardware, or yield issues under tight schedules. 6+ years of experience driving yield analysis and yield improvement for semiconductor, FPGA, SoC, or complex hardware products. 6+ years of data analysis experience using Python, JMP, or equivalent Preferred Qualifications Master’s or PhD in Electrical Engineering, Electronics, Physics, or related field. Strong background in analog and mixed-signal debug Familiarity with fault isolation (FI) and failure analysis (FA) techniques Exceptional technical communication skills; capable of translating highly technical, multi-disciplinary debug data into clear risk assessments and action plans for leadership. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. About Altera Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet. Don't see the dream job you are looking for? Click "Get Started" below to drop off your contact information and resume and we will reach out to you if we find the perfect fit.

Responsibilities

Lead cross-functional taskforces to resolve critical NPI hardware blockers and silicon issues across analog, mixed-signal, and power domains. Define debug strategies, analyze yield data, and present root-cause findings and recovery plans to executive leadership.