Staff/Senior Staff Verification Engineer at indie

Rabat, Rabat-Salé-Kénitra, Morocco -

Full Time

Start Date

Immediate

Expiry Date

18 Feb, 26

Salary

0.0

Posted On

20 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Digital Design Verification, SoC Verification, IP Verification, SystemVerilog, UVM, C Programming, Scripting Languages, Simulation Tools, Verification Methodologies, HW/SW Co-verification, Multi-mode Simulation, Emulation, Formal Verification, Power-aware Verification, Gate-level Simulation, Mentoring

Industry

Semiconductor Manufacturing

Description

Imagine being part of a team that’s redefining the future of mobility—where your ideas don’t just sit in a lab but power next-generation technology. At indie, we are developing cutting-edge semiconductors, photonics, and radar sensors and systems for automotive, industrial, and adjacent markets. Our innovations are at the heart of advanced intelligent sensing and user experience applications, pushing the boundaries of what’s possible. If you're passionate about groundbreaking technology and want to make a real impact alongside a fast-paced team that thrives on creativity and collaboration, we’d love to have you on board! We are seeking a highly skilled and motivated Staff/Senior Staff Design Verification Engineer to be a hands-on technical contributor on SoC, subsystem, and IP development projects. In this role, you will architect, specify, and lead the implementation of verification projects using high-level verification languages and methodologies. This role covers the entire verification lifecycle, from planning through coverage closure, and requires close collaboration with ASIC/SoC project leaders and cross-functional teams in a multi-site development environment. Key Responsibilities You will be part of the ASIC Verification Team, contributing to the development of indie’s SoC and platforms. As a Staff Design Verification Engineer, you will play a pivotal role in architecting and executing verification strategies for complex IPs and subsystems. Your responsibilities will include: · Define and drive verification plans based on design specifications and architecture documents. · Develop and maintain test benches using SystemVerilog/UVM or other advanced verification methodologies. · Lead verification efforts for complex IP blocks or subsystems, including planning, execution, and reporting. · Architect and implement complete verification environments and methodologies. · Perform functional, regression, and coverage analysis to ensure verification completeness. · Analyze customer technical requirements and propose effective verification solutions. · Mentor and develop team members, encouraging a highly creative and innovative environment. · Stay current with industry advances in verification technologies, methodologies, and processes. · Coordinate and communicate with cross-functional teams to define and execute verification strategies. · Participate in post-silicon validation and debug as needed. · Interview candidates and assist in recruitment activities. Qualifications & Skills Success in this role requires a solid background in digital design verification and hands-on experience with complex SoC or IP projects. Key qualifications include: · Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field. · 5+/8+ years of experience in SoC, subsystem, or IP verification in a team environment. · Solid understanding of digital design fundamentals, SoC architecture, and verification methodologies. · Experience with ARM-based SoC verification, including co-verification with firmware. · Strong expertise in C, SystemVerilog, and scripting languages (Python, Perl, Tcl, etc.). · Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). · Familiarity with protocols such as AMBA (AXI, AHB, APB), SPI, I2C, PCIe, MIPI, SD/eMMC, Ethernet, or DDR. · Familiarity with Jira for bug and task tracking, and Jama or similar tools for requirement management. · Solid understanding of verification methodologies including C-driven verification, coverage-driven verification, and UVM. · Exposure to HW/SW co-verification, multi-mode simulation, and emulation. · Proven record of delivering optimized design solutions and leading verification efforts. · Experience with formal verification (model checking, CDC), power-aware verification (UPF), and gate-level simulation is a plus. Attributes In addition to technical expertise, we value strong interpersonal and leadership qualities. The ideal candidate will demonstrate the following attributes: · Ability to respond to changing priorities quickly and work under pressure. · Strong attention to detail and self-motivation. · Team player with the ability to work independently and take initiative. · A self-starter who can identify verification gaps, propose improvements to the methodology, and implement efficient solutions. · Strong verbal and written communication skills to work effectively with cross-functional teams, including RTL design, architecture, and software. · A demonstrated desire and ability to mentor and grow junior verification engineers on the team. indie Semiconductor and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Concerning agencies: indie Semiconductor does not accept unsolicited resumes and will not be responsible for fees related to such.

Responsibilities

You will architect and execute verification strategies for complex IPs and subsystems. This role covers the entire verification lifecycle, requiring close collaboration with ASIC/SoC project leaders and cross-functional teams.