Staff Signal Integrity Design Engineer (Experience in LPDDR5) at Advanced Micro Devices, Inc

George Town, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

23 Feb, 26

Salary

0.0

Posted On

25 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Signal Integrity, Electromagnetic Modeling, Post-Silicon Measurement, Channel Optimization, Power Delivery Network Simulation, I/O Driver/Receiver Modeling, Behavioral Modeling, High-Speed Digital Logic, Analog Simulation, 3-D Modeling, Measurement Tools, Low-Voltage Swing Signaling, System-Level Timing Analysis, High-Speed Board Design, Silicon Design, Board Design

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As Signal Integrity Design Engineer, you will be responsible for SI specification definition, modeling, analysis and verification for products. You will be part of an engineering team to work on the current and next generation product performance verifications. You will lead/participate projects involving the modeling, design, verification, measurements of Signal Integrity of current and future AMD server products. You will work closely with multiple teams across IC Design, Layout, Packaging, Board, Product Engineer, Test Development, Application, Technical Service and Software to address the SIPI requirement from die, package to board level. Your specific responsibilities will include but not limited to the following: THE PERSON: You will provide technical supervision or mentoring to junior engineers and influence others as a subject matter expert. A successful candidate is one who can drive technical decisions independently, has accountability for accuracy, reliability and completeness of assignment results critical to the project’s success. This role allows the opportunity to influence technical decisions that have a significant impact on multiple products or the product line. KEY RESPONSIBILITIES: Work closely with cross-functional team and internal working group on current and next gen Server’s platform in meeting signal integrity in HVM solution space Electromagnetic modeling of 3-D structures including vias, connectors, sockets Verify and correlate post-silicon measurement against spec and collaborate fixes if needed to feedback on the next derivation silicon. Collaborate with working group leads for signal measurement test plans and review of measurement results. Deliver channel optimization (board and package), model creation and verification and simulate the overall performance to meet the channel performance. Document reports and BKM for future references. Be part of the team to develop and enhance next generation product and methodology Board/system-level power delivery network AC+DC simulation for low voltage/high-current supplies. Work with external and internal IP providers to ensure IPs performance and their proper functionality in our products. System-level signal integrity simulations of future LPDDR5, DDR5 memory bus including silicon IO, package, and board. System-level signal integrity simulations of future high-speed SERDES links such as USB-4, PCIe6, xGMI/CXL, etc. including silicon IO, package, and board. Resolve challenges in the areas of high speed board design, power and analog. PREFERRED EXPERIENCE: Transmission line theory and microwave engineering concepts such as Sparameter, etc. Low-voltage swing signaling technologies. System-level timing analysis considering effects from silicon IO, package, and board. I/O driver/receiver modeling for state-of-the-art high-speed digital logic. In-depth knowledge of I/O buffer modeling, specifically behavioral (IBISlike) modeling for high speed digital logic. Deep expertise in at least one of the following: PCIeX Physical layer, LPDDR4/5, Power delivery design, 100+Gig interfaces. Hands on experience in either Silicon design or board design will be highly advantageous. High motivation to continuously learn and resolve new challenges People skills and team spirit Expertise in analog simulation with Seasim, S2eye, Hspice, ADS, ANSYS, or other toolsets. Expertise in 3-D modeling with ANSYS HFSS/Q3D and 2.5-D with ANSYS SIWAVE. Expertise with DSO, TDR, VNA, ParBERT measurement tools/techniques. ACADEMIC CREDENTIALS: BS-EE or MS-EE with 8+ years of proven experience in high- speed digital bus simulation and high-speed board-level design LOCATION: Penang, Malaysia #LI-JK1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Responsibilities

As a Signal Integrity Design Engineer, you will define specifications, model, analyze, and verify signal integrity for AMD products. You will collaborate with cross-functional teams to ensure performance verification and address SIPI requirements from die to board level.