Staff VLSI Design Engineering (SOC Verification, System Verilog, UVM)with 8 at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

13 Oct, 26

Salary

0.0

Posted On

15 Jul, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SystemVerilog, UVM, VLSI Design Verification, C, Verilog, Xcellium, Verdi, JasperGold, SVA, Functional Coverage, SoC Verification, Formal Verification, Root-Cause Analysis, Test Planning, AI/ML Automation, NAND Flash Memory

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are seeking an experienced Principal Engineer, VLSI Design Engineering to lead verification efforts for complex IP blocks and fullchip designs. In this role, you will drive functional verification closure, mentor engineering teams, and collaborate across multiple disciplines to ensure design quality and silicon success. Key Responsibilities: Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP blocks, sub-systems, and SoC designs Design and implement verification environments using industry-standard UVM (Universal Verification Methodology) frameworks Develop reusable and scalable verification components, including bus functional models, monitors, checkers, and scoreboards Drive functional coverage-driven verification closure and ensure comprehensive design validation including Functional Coverage planning, development, debug and closure Develop and maintain System Verilog Assertions (SVA) for design verification, including coding, porting, and maintenance activities Collaborate with design architects, RTL designers, and post-silicon validation teams to ensure seamless verification integration Create and optimize verification automation tools and scripts to enhance design and verification productivity Investigate, debug, and perform root-cause analysis of design failures through cross-functional team collaboration Mentor junior engineers and contribute to the continuous improvement of verification methodologies and best practices Qualifications Required Qualifications: 7 to 11 years of relevant experience in VLSI design verification Bachelor's degree in Electronics and Communication Engineering (ECE), VLSI, or Electrical Engineering; Master's degree preferred Advanced proficiency in C, Verilog, SystemVerilog, and UVM (Universal Verification Methodology) Hands-on experience with industry-standard verification tools including Xcellium, Verdi, and JasperGold formal verification tools Demonstrated expertise across the complete verification lifecycle, including planning, testbench development, test case development, regression management, coverage analysis, debugging, and sign-off Proven ability to lead technical projects and manage stakeholder relationships effectively Bring in AI/ML/Automation based initiatives Excellent written and verbal communication skills with demonstrated ability to adapt to dynamic project requirements and deliver results under challenging schedules Preferred Qualifications: Experience with NAND flash memory protocols and memory design verification Track record of mentoring junior engineers and contributing to process improvements Experience with formal verification methodologies and assertion-based verification Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: VLSI Engineering Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP

Responsibilities

Lead the development of verification strategies and UVM environments for complex IP blocks and SoC designs. Drive functional coverage closure and mentor junior engineers to ensure silicon success.