Storage Design Verification Engineer at Apple

, , Israel -

Full Time

Start Date

Immediate

Expiry Date

09 May, 26

Salary

0.0

Posted On

09 Feb, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SoC Verification, IP Verification, SoC Architecture, Verification Flows, SystemVerilog, UVM, Scripting, Programming, Perl, Python, C, C++, TCL, Storage IPs, Formal Methods, Hardware Acceleration

Industry

Computers and Electronics Manufacturing

Description

Imagine what you could do here. At Apple, new ideas have a way of becoming great products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple products. In this visible role, you will be responsible for defining DV methodologies, test-bench infrastructure and project execution for the next generation MSP (Memory Signal Processing) IPs to enable state of the art storage solutions for Apple products line. DESCRIPTION You will develop verification test plans, test benches, tools and infrastructure, protocol monitors and agents, and coverage driven stimulus in UVM. Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market. Apply deep system level understanding to find system architecture bugs, verifying the DUT at multiple levels - from block level to the entire IP and subsystem, with additional emphasis on power (NLP) and performance. You will work closely with the design, architecture, software, system and validation teams from the early stages of IP definition, to ensure timely delivery of quality designs. Involvement with Post Silicon Validation and other verification teams. MINIMUM QUALIFICATIONS 5+ years of experience in SoC or IP verification Advanced knowledge of SoC architecture/design, in-depth knowledge of verification flows and broad system view Expected to have a deep understanding and shown experience in advanced verification processes, including coverage driven and formal methods Extensive experience with SystemVerilog and UVM Experience with verification infrastructure development Scripting and programming experience using several of the following: Perl, Python, Verilog, SystemVerilog, C, C++, and TCL PREFERRED QUALIFICATIONS Knowledge of storage IPs and control oriented design - an advantage Knowledge of formal, hardware acceleration – an advantage BS.c/ MS.c in EE/CE

Responsibilities

You will be responsible for defining DV methodologies, test-bench infrastructure, and project execution for next-generation MSP IPs. You will develop verification test plans, test benches, tools, and infrastructure to ensure timely delivery of quality designs.