Start Date
Immediate
Expiry Date
23 Feb, 26
Salary
0.0
Posted On
25 Nov, 25
Experience
0 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
Digital Design, Design Verification, Gate-Level Simulation, Verilog, System-Verilog, UVM, Perl, Python, Unix Shell, TCL, Advanced Verification Techniques, Constrained Random Generation, Functional Coverage, Assertions, Industry Standard Protocols, PCIe, Ethernet
Industry
Computer Hardware Manufacturing