SYN/STA Engineering Intern (Optical PHY) at Marvell Technology

Ho Chi Minh City, , Vietnam -

Full Time

Start Date

Immediate

Expiry Date

04 Apr, 26

Salary

0.0

Posted On

04 Jan, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Logic Synthesis, Static Timing Analysis, Digital Design, ASIC Design Flows, Constraint Development, Synthesis Optimization, Timing Closure, EDA Tools, Programming, Scripting, Problem-Solving, Analytical Skills, Communication Skills, Team Collaboration, Ownership, Accountability

Industry

Semiconductor Manufacturing

Description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Central Engineering – Optical PHY (CE-OPHY) team designs high-speed and optical transceivers for communication infrastructure in long-haul, metro and datacenter. We address the bandwidth, capacity and power issues faced by cloud computing, mega data centers that powers the social media giant platforms. Our innovative approaches have resulted in the company’s products being first to market in many of key areas, developing the most advanced chips and subsystems solutions to address the ever-increasing demand of higher data rates driven by video-on demand, gaming and other real time data streams. We are seeking talented individuals to work on solving technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity. As a member of a dynamic CE-OPHY team, the candidate will be responsible for designing circuits used for high-speed optical transceivers. The member will have an opportunity to work in deep submicron process and collaborate with the team on next-gen high-speed optical transceivers. This is more than a typical internship—it’s a launchpad of your career as you are expected to not only learn and develop your technical competencies, but also integrate into Marvell's core behaviors and working culture that drives innovation and leading innovation in the industry. You’ll gain hands-on experience, receive mentorship from industry leaders, and contribute to real projects that drive Marvell’s product and R&D roadmap. What You Can Expect Train and learn to perform logic synthesis at sub-system or top level for multi-million gate ASIC projects. Train and learn to perform RTL Lint, CDC, LEC and design functional ECO to ensure design correctness and quality. Train and learn to perform constraint validation, STA signoff, timing ECOs to achieve timing closure. Collaborate with logic design (RTL) engineer and physical design (PD) engineers to resolve logic, timing, power and physical implementation issues. Assist with managing schedules and support cross-functional engineering efforts across design teams. Assist with developing, enhancing, and maintaining Synthesis and STA scripts, as well as related automation flows. Contribute to the continuous development of IC design flows and methodologies. Why This Internship Matters This internship will give you: Real project experience in one of the world’s leading chip design environments Exposure to Marvell’s core technologies, toolchains, and product workflows A mentorship path that could evolve into a full-time role or thesis opportunity Your Path Forward Many of our interns go on to become key contributors and technical leaders within Marvell. If you’re dreaming of a career that contributes to the significant growth of AI Accelerate Infrastructure—this is where you start. What We're Looking For Currently pursuing 3rd or 4th year of BS in Electrical Engineering/Computer Engineering, or related fields, with knowledge of digital design. Early-stage Master education level is highly recommended. Solid foundation knowledge of logic synthesis and static timing analysis (STA) for ASIC/SoC designs. Familiar with ASIC design flows, including Front-End design, DFT and Physical Design (PnR). Familiar with constraint development, synthesis optimization, and timing closure across multiple design stages. Familiar with industry-standard EDA tools, including logic synthesis (Synopsys DC, Cadence Genus), logical equivalence checking (Formality, Conformal), and STA (PrimeTime, Tempus). Familiar with programming and Scripting skills in language like PERL/Python, TCL & C/C++, in a Unix-based environment. Strong problem-solving and analytical skill. Confident in written and verbal English communication skills. Self-motivated and eager to learn new skills, tools, IPs, and design flows. Collaborative team player with strong sense of ownership and accountability, willing to take on new challenges. Experience in the following is a plus: RTL coding, Design verification DFT methodologies SERDES, Data Communication, Communication Standards (IEEE, Ethernet protocols) Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-HP1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

Responsibilities

The intern will be responsible for designing circuits used for high-speed optical transceivers and will collaborate with the team on next-gen optical transceivers. They will also assist in managing schedules and support cross-functional engineering efforts.