WE ARE LOOKING FOR STRONG HANDS-ON EXPERIENCE IN 3 AREAS

• SDC:/Design Constraints and STA: Timing Analysis (PrimeTime) : Very good knowledge in writing Timing Constraints with these tools
• Digital Circuits: Person should be very strong in Design Fundamentals so can make right changes in RTL as needed
• Bridge: He needs to act as a bridge between Design & Physical Design team and provide solutions to meet timings through constraints
• PD Tools: Nice to have but not must have floor-planning and P&R flow work
  Job Type: Contract
  Pay: $70.00 - $75.00 per hour
  Expected hours: 8 per week

Experience:

• STA Developer: 10 years (Required)
• SDC Developer: 10 years (Required)
• ASIC: 10 years (Required)
• Static Time Analysis: 10 years (Required)
• Block chip SDC: 10 years (Required)
• Full Chip SDC: 10 years (Required)
• Prime Time: 10 years (Required)
• Tempus: 10 years (Required)
• Digital Design: 10 years (Required)
• TCM: 10 years (Required)
• Timing Constraint Manager: 10 years (Required)
• Spyglass: 9 years (Required)
• Synthesis tools: 10 years (Required)
• Verilog: 10 years (Required)

Work Location: In perso

• Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
• Creating fullchip clocking diagrams and related documentation.