System Integration Validation Engineer at Altera

, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

28 Jun, 26

Salary

0.0

Posted On

30 Mar, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Coding, Simulation, Logic Design, Architecture Definition, Microarchitecture Definition, Logic Optimization, IC Validation Methodologies, Test & Measurements, FPGA Architecture, Verilog, System Verilog, Python, Tcl, C-Programming, VBA, HTML

Industry

technology;Information and Internet

Description

Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IP-SoC handoff. Qualifications: Good knowledge in IC validation methodologies and experience in conducting test & measurements for various IC timing/frequency/current/ voltage parameters Good knowledge in FPGA architecture, Verilog/System Verilog is an added advantage Experience in developing programming languages such as Python, tcl, C-programming, VBA, HTML etc. is an added advantage Experience in handling various high speed test and measurement equipment such as ATE tester, high bandwidth real time/sampling oscilloscope, high frequency pulse/signal , power supply is an added advantage Job Type: Regular Shift: Shift 1 (Malaysia) Primary Location: Penang 15, Penang, Malaysia Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. About Altera Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet. Don't see the dream job you are looking for? Click "Get Started" below to drop off your contact information and resume and we will reach out to you if we find the perfect fit.

Responsibilities

Develops logic design, RTL coding, and simulation for IP blocks, participating in defining architecture and microarchitecture features. Applies strategies and tools to optimize logic for power, performance, area, and timing goals while reviewing verification plans and resolving failing tests.