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Job Description:

Microchip Technology Inc. has a Technical Staff Engineer-Digital Design opening based in San Jose, CA. As a member of Microchip’s FPGA design engineering team, you will be responsible for the definition, design and integration of interfaces between the global buses and the different blocks in the FPGA such as fabric, I/Os, NOCs, memories, etc. The successful candidate will also be responsible for the below.

• Collaborate with cross-functional teams to establish requirements and specifications for interface logic between global buses and FPGA components such as fabric, I/Os, Network-on-Chip (NoC), and memory blocks.
• Develop efficient, high-performance digital designs for these interfaces, ensuring compatibility and seamless communication between the FPGA’s internal components.
• Translate design and timing requirements provided by the architects into Verilog code ,and implement and test the RTL code.
• Partner with architects and lead designers to identify and implement improvements to enhance the efficiency, speed, and reliability of the interfaces.
• Provide support for post-silicon integration, bring-up, and validation.
• Effectively present technical information to small engineering teams.
• Maintain regular communication with the architecture, design and verification team across multiple locations to resolve issues, update status and address technical challenges.
• Stay updated with the latest industry trends and technologies to continuously improve design processes.

Requirements/Qualifications:

• Bachelor’s or Master’s in Electrical Engineering or Computer Science
• 12+ years of experience including several product cycles of successful ASIC and SoC development.
• Expertise in areas such as AMBA bus protocols, CPU and memory architecture.
• Familiarity with chip bus controllers and flash controllers, PCI-e, DDRx is a plus.
• Proficiency in Verilog, System Verilog, and testbench generation and simulation.
• Hands-on experience in synthesis and PnR.
• Proven skills in scripting, managing simulation queues, and data capture with ability to present findings using Microsoft Office tools, including Excel.
• Capability to support layout, verification, timing characterization, and software model developers.
• Strong analytical, oral and written communication skills
• Able to create clean, readable presentations.
• Self-motivated and proactive team player.
• Ability to meet schedule requirements effectively.

Travel Time:
0% - 25%
Physical Attributes:
Feeling, Hearing, Seeing, Talking, Works Alone, Works Around Others
Physical Requirements:
15% standing, 15% walking, 70% sitting, 100% In doors; Usual business hours
Pay Range:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:
Benefits of working at Microchip

The annual base salary range for this position, which could be performed in California, is $88,000 - $232,000.*

• Range is dependent on numerous factors including job location, skills and experience.

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the
Know Your Rights: Workplace Discrimination is Illegal Poster
.
To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes

• Collaborate with cross-functional teams to establish requirements and specifications for interface logic between global buses and FPGA components such as fabric, I/Os, Network-on-Chip (NoC), and memory blocks.
• Develop efficient, high-performance digital designs for these interfaces, ensuring compatibility and seamless communication between the FPGA’s internal components.
• Translate design and timing requirements provided by the architects into Verilog code ,and implement and test the RTL code.
• Partner with architects and lead designers to identify and implement improvements to enhance the efficiency, speed, and reliability of the interfaces.
• Provide support for post-silicon integration, bring-up, and validation.
• Effectively present technical information to small engineering teams.
• Maintain regular communication with the architecture, design and verification team across multiple locations to resolve issues, update status and address technical challenges.
• Stay updated with the latest industry trends and technologies to continuously improve design processes