Technologist, ASIC Development Engineering (Lead Full chip SOC Sign-off & E at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

28 Jun, 26

Salary

0.0

Posted On

30 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

EMIR Closure, SOC Sign-off, IR Drop Analysis, Electromigration Analysis, Physical Design, Synthesis, ICC2, Fusion Compiler, Ansys Redhawk, Primetime, Shell Scripting, Python Scripting, Perl Scripting, TCL Scripting, Technical Leadership, DFx

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description The candidate to have a passion for complex processor architecture, digital design, and verification in general. The candidate should be team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. The candidate should have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: - EMIR closure at Tile /Partition/Subsytem/SOC level on a particular node Ownership of EMIR Flow & Signoff Drive EMIR closure for design blocks and full-chip integration. Align EMIR analysis phases with PD milestones (INIT, PREFINAL, FINAL). Ensure compliance with signoff limits provided by SIPI team for given technology node Ability to analyze EMIR violations and propose implementation choices. Familiarity with DFx and scan architecture for EMIR considerations. Technical Leadership Define EMIR signoff strategy, including IR drop and electromigration analysis. Review floorplan, clocking, and bus structures for IR hotspots. Coordinate bump allocation and power rail alignment with integration teams. Collaboration & Coordination Work closely with block owners, PD team, and integration team to execute EMIR runs. Conduct EMIR run reviews and debug sessions with stakeholders. Methodology & Flow Development Maintain and improve EMIR flow Engage with SIPI team for current profile analysis and CPA/CPM models PREFERRED EXPERIENCE: Minimum 13+ years of relevant work experience. Expertise in Synthesis , ICC2/ FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools. Expertise in Signoff tools like Ansys Redhawk/RHSC on EMIR, PT-PX for Power signoff and Primetime for Timing Should have worked as a go to person or technical lead for at least few full chip projects. Strong technical leadership and ability to mentor/guide/coach design engineers to achieve and deliver project goals. Strong inter-personal skills and ability to collaborate with teams spread across multiple geos. Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts. Must be using AI technologies in day to day problem solving Qualifications Bachelors or Masters degree in Electronics and communication engineering/Electronics and Electrical Engineering Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP

Responsibilities

The role involves owning the EMIR flow and driving closure at various levels (Tile, Partition, Subsystem, SOC) to ensure compliance with signoff limits, while also defining the overall EMIR signoff strategy.