Technologist, ASIC Development Engineering (RTL-to-GDSII SoC implementatio at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

06 Jun, 26

Salary

0.0

Posted On

08 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL-to-GDSII Implementation, SoC Implementation, Floor Planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, Sign-off, OCV, MM/MC Optimization, Multi-Power Designs, Static Timing Analysis, ECO Generation, Bump Planning, Physical Verification

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Position Overview: We are looking for a highly skilled and experienced individual for SoC PD lead position for driving SoC implementation efforts from RTL to GDSII. This role is pivotal within our talented team of engineers, ensuring that we meet our GDS release timelines, PPA requirements, and all sign-off criteria for our complex semiconductor designs. This role demands a profound technical understanding of the entire implementation cycle, from start to finish, as well as exceptional leadership skills. The successful candidate will work with various functional teams and must possess a strategic vision to drive continuous improvement in our methodologies and processes. Key Responsibilities: To be responsible for leading RTL-to-GDSII SoC implementation effort To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc. To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity. To ensure process compliance during project execution and enable / participate in technical discussions/reviews. To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations. Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow Foster a culture of innovation, collaboration, and continuous improvement - Qualifications - Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field - A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs Proven ability in technically leading a small/medium-sized team for executing projects preferred. Hands-on experience on the entire PD Flow from RTL to GDSII Should have a good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains. Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc) Exposure to static timing analysis fixes including automated ECO generation. Strong in areas on CTS, Power, Bump planning, Floorplan Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies. Library preparation in any environment (Synopsys, Cadence, etc) Working knowledge on Physical verification tasks at lower nodes (database merging/DRC/LVS/ERC/PERC/Antenna/ESD/LUP analysis/fixing) at block level/chip level The job would require complete ownership from RTL to GDS for complete SoC Exposure to IP Hardening for blocks like SERDES, USB PHY, PCIe, DDR will be an added advantage. Working knowledge of scripting languages like Perl and TCL will be considered a plus Candidate needs to be self-driven and confident in reporting the status and sharing technical results with customers. Must have the ability to present to senior management, work in a geographically dispersed team, and be aware of cross-cultural nuances. Should be able to define project milestones, identify risks, and call out mitigation plans. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP

Responsibilities

The role is responsible for leading the entire RTL-to-GDSII SoC implementation effort, ensuring GDS release timelines, PPA requirements, and all sign-off criteria are met. This involves collaborating with cross-functional teams, guiding team members, and driving continuous improvement in methodologies.