Technologist, ASIC Development Engineering at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

09 Mar, 26

Salary

0.0

Posted On

09 Dec, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC RTL Design, Verilog, System Verilog, SoC Architecture, AMBA Protocols, Power Intent Format, Timing Constraints, Scripting Languages, EDA Tools, Problem-Solving, Communication, Teamwork, Low-Power Design Techniques, Storage ASICs, High-Speed Interfaces, AI Tools

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Are you ready to push the boundaries of what's possible in technology? Join the trailblazers at Sandisk, as an ASIC RTL Design Engineer, you will be at the forefront of designing high-performance ASICs. By leveraging your expertise in RTL design and modern tools like GitHub Copilot, you will enhance the design process and productivity. You will collaborate with cross-functional teams to deliver groundbreaking solutions that meet our high standards of quality and performance Key Responsibilities: Innovate, implement, and verify RTL code for complex ASICs. Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers. Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab. Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process. Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution Lead design reviews and provide mentorship to junior engineers. Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution. Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design. Qualifications Qualifications Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience. Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog. Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug. Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must. Proficiency in scripting languages (e.g., Python, TCL) for automation. Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification). Strong problem-solving skills and the ability to thrive in a dynamic environment. Excellent communication and teamwork abilities. Preferred Qualifications: Experience in low-power design techniques and methodologies. Prior knowledge with storage ASICs is a plus. Familiarity with high-speed interfaces (e.g., USB, SD Express, Compact Flash, PCIe, DDR). Familiarity in leveraging AI tools, including GitHub Copilot, for design and development. Additional Information All your information will be kept confidential according to EEO guidelines.

Responsibilities

The role involves innovating, implementing, and verifying RTL code for complex ASICs while collaborating with cross-functional teams. The engineer will also lead design reviews and mentor junior engineers.