Technologist, Mask Design Engineering • Memory Technology at Sandisk

Seoul, , South Korea -

Full Time

Start Date

Immediate

Expiry Date

08 Jun, 26

Salary

0.0

Posted On

10 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Mask Layout Design, Peripheral Circuit, Layout Expertise, Signal Planning, Power Planning, Floor Planning, Full Chip Integration, Verification, Layout Quality, Layout Schedule, Mentorship, Technical Guidance, Virtuoso Layout Editor, Calibre DRC, Synopsys LVS

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are seeking a Technologist, Mask Design Engineering specializing in Memory Technology to join our innovative team in Seoul, South Korea. In this senior-level role, you will lead the mask layout design for peripheral circuit and working across global teams to enable successful tape‑outs. This role is intended for recognized technical leaders who combine deep layout expertise (STD/Block layout, signal/power planning, Floor Planning and full chip integration), strong verification skillset, and thinking, and who maintain both layout quality and layout schedule across projects. Furthermore, you are expected to take the lead in enhancing the overall capabilities of the team and improving layout design quality through mentorship and technical guidance provided to junior engineers. Qualifications Your Experience 10+ years of experience in IC layout virtuoso layout editer Calibre DRC Synopsys LVS Nice to have English skills Knowledge of Layout automation Experienced management or leading Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: Mask Design Engineering Work Location: Seoul Office--LOC_WDT_KR1101

Responsibilities

This senior-level role involves leading the mask layout design for peripheral circuits and collaborating across global teams to ensure successful tape-outs. The technologist is also expected to enhance team capabilities and improve layout design quality through mentorship and technical guidance for junior engineers.