Come and be part of a collaborative team environment that innovates and develops the latest IP solutions that enable the way the world designs.
As a SERDES Silicon Validation Engineer working in a lab environment, you will be responsible for product qualification and compliance to supported standards/specifications. You will be part of an R&D team developing high speed SerDes PHYs. We are looking for an engineer with theoretical knowledge and practical experience to contribute to the team. Our R&D test lab contains high speed equipment such as: 224Gb/s capable BERTs, 70 GHz Oscilloscopes, 80GHz Sampling Scopes, 67 GHz Network analyzer and 50 GHz TDR for SERDES test and debug.

REQUIREMENTS

• A Bachelor’s degree in electrical or electronics engineering or in an appropriate related engineering discipline with 5 years related experience in test engineering
• Analog IC circuit knowledge
• Software programming experience
• Knowledge and experience with Matlab and digital design
• Debugging skills
• PAM4 signaling, test and debug background
• Experience with IC Test and Validation of Mixed Signal, ADC/DAC and SerDes test circuits
• Experience with high speed test equipment including 70GHz oscilloscopes, 67GHz network analyzer, and High Speed BERTs for SerDes test and debug

• Work with a cross functional design team of analog designers, systems designers, application engineers, and customers to resolve problems and demonstrate product performance;
• Analyze and explain circuit behavior and circuit limitations in a testing and characterization environment;
• Define test requirements and methodologies to validate silicon under test against target specifications.
• Research and specify test equipment and components to support defined test plans and methodologies.
• Running characterization tests and creating test reports;
• Creating test boards and hardware solutions to support product validation;
• Writing software/scripts to automate tests and part control for product testing
• Debugging of electronic circuits; investigating product nonconformance.