Test Engineer, Automotive Robotics at Tenstorrent

Munich, Bavaria, Germany -

Full Time

Start Date

Immediate

Expiry Date

29 May, 26

Salary

0.0

Posted On

28 Feb, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Bring-up, Wafer Yield Management, Field Failure Analysis, System Requirements Translation, DFT Insertion, ATE Test Content, SLT Test Content, Foundry Interaction, OSAT Interaction, ATE Vendor Debugging, Cross Functional Role, Low Power Designs, Multiple Clock Domains, Test Strategy Definition, SiP Architecture, RISC-V CPU

Industry

Computer Hardware Manufacturing

Description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As part of Tenstorrent’s Automotive Robotics team, you will help design and deliver the core hardware modules inside our next generation chiplet based SoCs for automotive products. You will be the bridge between silicon design, DFT, OSAT partners, and customers to ensure our multi die SiP platforms meet aggressive performance, quality, and safety targets. This role is remote, based in Munich, Germany. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced with bringing ASICs from design phase through production ramp, managing wafer yield, and analyzing field failure rates. Able to translate system and safety requirements into concrete constraints on package architecture, DFT insertion, and ATE or SLT test content. Confident working directly with foundry, OSAT, and ATE vendors to debug issues. Comfortable working in a cross functional role that extends beyond DFT, including low power designs with multiple clock domains. What We Need Define test strategy for multi chiplet packages from initial silicon through high volume production. 10+ years of experience working across multiple teams and multiple companies to coordinate test, yield, and quality efforts. Feed lessons learned back into next generation SiP architectures, DFT strategy, and test content. What You Will Learn How to bring a SiP to high volume, automotive grade production. How chiplets, RISC V CPUs, AI accelerators, and die to die links come together in a unified automotive platform. How to trade off package architecture, DFT, and test cost to hit aggressive performance, quality, and reliability targets. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Responsibilities

The role involves defining the test strategy for multi-chiplet packages from initial silicon through high volume production, coordinating test, yield, and quality efforts across multiple teams and companies. Responsibilities also include feeding lessons learned back into next-generation SiP architectures, DFT strategy, and test content.