Timing Design Engineer at Apple

Melbourne, Florida, United States -

Full Time

Start Date

Immediate

Expiry Date

20 Jul, 26

Salary

0.0

Posted On

21 Apr, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC design, STA, Timing sign-off, Timing constraints, Primetime, Tcl, Perl, Synthesis, DFT, Backend methodology, SoC design, Signal integrity, Clock structure, Physical design, Timing closure

Industry

Computers and Electronics Manufacturing

Description

Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something. DESCRIPTION As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis. MINIMUM QUALIFICATIONS Bachelors of Science in Electrical Engineering. PREFERRED QUALIFICATIONS Proven knowledge of the ASIC design timing closure flow and methodology. 2+ years of experience in writing ASIC timing constraints and timing closure. Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues. Hands on experience in timing/SDC constraints generation and management. Proficient in scripting languages (Tcl and Perl). Familiarity with synthesis, DFT and backend related methodology and tools. Strong communication skills are a pre-requisite – you will be collaborating with many diverse groups at Apple. The ideal candidate will be a self-starter and highly motivated to be successful at Apple.

Responsibilities

You will be responsible for all aspects of SoC timing, including sign-off, flow development, and ownership of IP and block-level timing constraints. You will collaborate with RTL, CAD, and physical design teams to ensure timing closure and develop innovative constraints.