REQUIREMENTS:

• Bachelor or master’s in electrical/Electronic Engineering
• Proficient in using industry-standard EDA tools (Synopsys, Cadence)
• With 6 - 10 years of experience in IC design
• Strong communication skills for effective collaboration with front-end and back-end design teams
• Excellent analytical skills for identifying and resolving design issues

• Prepare clean and optimized gate-level netlists.
• Develop and validate the design constraints (SDC).
• Support Design for Test (DFT) requirements.
• Conduct formal equivalence checking.
• Support definition and validation of power intent using UPF.
• Provide inputs to support floor planning activity.
• Assist in defining and validating the Clock Tree architecture.
• Perform Static Timing Analysis (STA) at pre- and post-layout stages.
• Implement and validate ECOs.
• Drive and contribute to the continuous improvement of middle-end implementation flows and methodologies.