ABOUT CELESTIAL AI

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.

QUALIFICATIONS

• Bachelor’s degree in electrical engineering or related discipline with at least 4+ years of relevant experience; Master’s degree preferred.
• Strong proficiency in SystemVerilog and deep expertise in UVM methodology, including constrained random testing techniques.
• Solid scripting skills, particularly in Python, to automate verification tasks and infrastructure.
• Proven track record achieving thorough functional and code coverage, demonstrating high-quality verification outcomes.
• Excellent communication skills, with the ability to effectively collaborate across diverse technical teams.
  LOCATION: Santa Clara, CA
  For California Location:
  As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $175,000.00 - $200,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.
  We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.
  Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.
  

  LI-Onsit

ABOUT THE ROLE

We are seeking an experienced Verification Engineer with strong expertise in SystemVerilog and UVM methodologies to join our collaborative team. You will play a key role in defining verification strategies, developing robust UVM environments, and enhancing our overall verification infrastructure. Our team works on complex IP and SoC verification, including emulation, AMS Co-Simulation, and industry-leading UVM methodologies.

ESSENTIAL DUTIES AND RESPONSIBILITIES

• Develop UVM testbenches, stimulus, and constraints.
• Establish detailed test plans ensuring complete functional and code coverage.
• Lead rigorous testbench reviews involving designers, architects, and software engineers to uphold verification quality.
• Ensure that our SoCs are functionally correct by developing SystemVerilog/UVM verification environments
• Create detailed verification plans for block-level, IP, and SoC-level projects.
• Collaborate closely with ASIC and SoC design teams to manage milestones and ensure timely deliverables.
• Drive continuous improvement of verification methodologies and processes.
• Build and optimize verification infrastructure to enhance efficiency and effectiveness.
• Coordinate with software and emulation teams to ensure first-pass tapeout success.