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Verification Engineer at Quantum Machines

Tel Aviv, Tel-Aviv District, Israel -

Full Time

Start Date

Immediate

Expiry Date

01 Apr, 26

Salary

0.0

Posted On

01 Jan, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Verification, UVM, System Verilog, Verification IPs, PCIe, DDR, AXI, HW/SW Interaction, C, C++, Python, System C

Industry

Computer Hardware Manufacturing

Description

Quantum Machines is a global leader in control systems for quantum computing, a field on the verge of exponential growth. Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands. At the core of QM lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers. Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field. We are looking for a Verification Engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base. The Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists. Responsibilities: Practicing the full range of verification aspects Creating a verification environment from scratch (drivers, monitors, coverage...) VIP (DDR/PCIe/AXI) integration Defining verification sequences via a complex control-flow constraint set System understanding of a full-stack product with strong HW-SW coupling Reference model integration Test plan definition Defining verification flows and creating the proper infrastructure to support it Requirements: 3- 5 years experience. Ability to ramp up verification environments from scratch Experience with UVM, System Verilog - Advantage Knowledge of Verification IPs and protocols (PCIe, DDR, AXI) Good understanding of HW/SW interaction- Advantage Knowledge in C/C++/Python/System C - Advantage Requirements null Preferred Skills null

Responsibilities

The Verification Engineer will practice the full range of verification aspects, create a verification environment from scratch, and define verification flows. They will also collaborate closely with engineers from other disciplines and quantum physicists.