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VLSI Design Verification Engineer_1 at Ambarella
Hsinchu, , Taiwan -
Full Time

Start Date

Immediate

Expiry Date

18 Oct, 26

Salary

0.0

Posted On

20 Jul, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

SystemVerilog, UVM, Verilog, C, C++, Perl, Python, Digital Design, Computer Architecture, VLSI Verification, Assertion-Based Verification, Coverage-Driven Verification, SoC Verification, Debugging, Analytical Skills, Problem-Solving

Industry

Semiconductor Manufacturing

Description
AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Job Description We are looking for talented engineers to join our VLSI Verification team. You’ll work on next-generation SoCs, applying advanced verification methodologies (SystemVerilog/UVM, coverage-driven, assertion-based) and leveraging AI-assisted tools to accelerate testplan writing, assertion development, and debug. Responsibilities • Develop and execute verification plans for complex SoCs/IPs • Build testbenches, assertions, and coverage models • Collaborate with architects, designers, and post-silicon teams • Ensure correctness and reliability of cutting-edge designs Why Join Us • Cutting-edge verification with AI-powered flows • Work alongside global world-class engineers • Accelerated growth in a learning-driven culture If you are smart, curious, and eager to learn, join us and shape the future of silicon innovation! Qualifications • Bachelor’s, Master’s, or PhD in EE/CS or related field • Strong background in digital design and computer architecture • Experience with SystemVerilog/UVM/Verilog/C/C++ (script with Perl/Python is a plus) • Strong debugging, analytical, and problem-solving skills
Responsibilities
Develop and execute verification plans for complex SoCs and IPs using advanced methodologies. Build testbenches, assertions, and coverage models while collaborating with architects and designers to ensure design reliability.