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JUNIOR DESIGN VERIFICATION ENGINEER

We are seeking a motivated Junior Design Verification Engineer to join our hardware team. You will assist in verifying digital designs through simulation, testbench development, and debugging. Working under senior engineers, you’ll help ensure design functionality, coverage, and compliance with specifications.

REQUIREMENTS:

• Bachelor’s degree in Electrical/Computer Engineering or related field
• Familiarity with Verilog/SystemVerilog
• Understanding of digital logic and basic verification concepts
• Strong problem-solving and communication skills

• Develop and maintain SystemVerilog/UVM-based testbenches
• Write and execute test cases for functional verification
• Debug RTL and simulation failures
• Support regression runs and coverage analysis
• Collaborate with design, DFT, and validation teams