Wireless RTL Design Engineer at Apple
Sunnyvale, California, USA -
Full Time


Start Date

Immediate

Expiry Date

21 Nov, 25

Salary

190900.0

Posted On

21 Aug, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Design Techniques, Systemverilog, Programming Languages, Logic Design, Communication Skills

Industry

Information Technology/IT

Description

Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a critical impact on getting functional products to hundreds of millions of customers quickly. Will you join us and do the work of your life here?

DESCRIPTION

In this role, you will develop signal processing intensive design for wireless communication SoCs, including: • Writing specifications and other documents based on MATLAB/C system model. • Microarchitecture definition. • Running tools to ensure lint-free design. • Collaboration with algorithm and software team to ensure performance and power efficiency.

MINIMUM QUALIFICATIONS

  • BS degree is required.
  • Have taken relevant courses such as DSP/wireless communications/machine learning and VLSI logic design.
  • Understanding of DSP communication algorithms and trade-offs between performance and complexity.
  • Good knowledge in modern logic design techniques.
  • Excellent communication skills and self-motivation.
  • Familiar with Verilog/Vhdl and MATLAB/C programming languages.

PREFERRED QUALIFICATIONS

  • MSEE/PhD degree.
  • Familiar with SystemVerilog.
  • Exposure to chip tapeout or FPGA flow.

How To Apply:

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Responsibilities

Please refer the Job description for details

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