A SUCCESSFUL CANDIDATE WILL HAVE PROVEN EXPERIENCE DEMONSTRATING THE FOLLOWING SKILLS AND BEHAVIORAL TRAITS:

• Excellent communication skills, both written and verbal.
• The ability to work independently and as part of a team.
• Strong organizational skills and attention to detail.
• The ability to manage multiple tasks and prioritize effectively.
• Experience with developing and executing test plans in Silicon products.
• Strong understanding of cache coherence protocols and their applications.
• Familiarity with performance monitoring tools and techniques.
• Knowledge of hardware and software debugging tools.
• Proficiency in programming languages such as C/C++ and Python.
• Windows/Unix experience
• Strong problem-solving skills and the ability to analyze complex systems.
• The ability to interpret test results and identify root causes of issues.
• Familiarity with Intel’s Cache Coherent protocol.
• Knowledge of industry standards and best practices for system validation.
• Continuous Learning.
• Willingness to stay updated with the latest advancements in Xeon related technologies.
• Proficiency in Cache Coherence concepts.

QUALIFICATIONS

Minimum Qualifications:

Minimum qualifications are required to be initially considered for this position.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 4+ years of experience in Post-Silicon Coherent protocols validation.
• 4+ years of debug experience of Coherent protocols and related features.
• 4+ years of experience with system-level validation.
• Advanced experience with cross-functional teams including architecture, design, and software engineering.
• Advanced experience supporting validation of multiple products in parallel.

• Defines, develops, and performs functional validation for integrated SoCs, focusing on validation of IP integration, interaction between IPs, and system level features.
• Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met.
• Reviews proposed design changes to assess impact on validation plans, tasks, and timelines.
• Develops SoC validation methodologies, validation test plans, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis. Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC issues.
• Tests interactions between various SoC features using validation infrastructure.
• Develops post silicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing.
• Publishes SoC validation reports summarizing all validation activities performed, reviews results, and communicates to relevant teams.
• Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for SoC interfaces and to meet desired product specifications.
• Develops content to create or increase specific IP interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom OS builds).
• Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, FPGAs) to ensure silicon readiness.