Why Apple? We live in a mobile and device-driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. Apple is meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that commitment. The success we are striving will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problems in new ways. If that sounds like the kind of environment that you find intriguing, then let’s talk. In this role, you will be a key member of our team in Munich. You will be leading a local team working on timing and constraints development, synthesizing RTL code and delivering netlist to the backend team. You will be working with advanced technologies and directly collaborating closely both with RTL designers and Physical Designers, towards completion of Analog Mixed Signal IPs.

DESCRIPTION

As a Lead of a local Timing team, you will be responsible for all aspects of SoC design in terms of timing and synthesis. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will also closely collaborate with RTL designers to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical Design team to close and sign-off timing. You will come up with ideas and plans to verify timing constraints, innovate timing constraints and flow to facilitate timing closure, improve synthesis result, improve methodologies and ensure that your team delivers the required collaterals in time with high quality.

MINIMUM QUALIFICATIONS

• We look forward to hearing your detailed knowledge of the ASIC design timing closure flow and methodology, as this role requires. Ideally, you will have:
• Relevant years of experience in writing ASIC timing constraints and timing closure.
• Validated experiences in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations & signal integrity related issues.
• Hands-on experiences in timing/SDC constraints generation and management.
• Proficient in scripting languages (Tcl and Perl).
• Have good knowledge in synthesis, DFT and backend-related methodology and tools.
• Excellent communication and interpersonal skills and always enthusiastic to collaborate with diverse teams.
• Ability to work well in an international team, take responsibility, perform under strict deadlines and motivate self to balance priorities.
• Relevant experience in managing technical teams, ideally in the area of ASIC design.
• Proficiency in English language is required

PREFERRED QUALIFICATIONS

• Bachelor’s/Master’s Degree in Electric Engineering with relevant experience.Apple is an Equal Opportunity Employer committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.
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Please refer the Job description for details