SKILLS & EXPERIENCE

• 7+ years of hands‑on digital design for high‑performance ASICs or SoCs, including ownership of at least one product that processes a continuous real‑time data stream.
• Proven success closing timing on multi‑hundred‑MHz to multi‑GHz clock domains and integrating high‑speed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar).
• Expertise with industry‑standard EDA flows: RTL synthesis, CDC/RDC, STA, power‑intent (UPF/CPF), lint, and gate‑level simulation.
• Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the lab.
• Proficiency using MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed‑point analysis and test‑vector generation.
• Solid grounding in digital signal‑processing concepts, computer‑architecture fundamentals and semiconductor device physics.
• Excellent communication and cross‑functional collaboration abilities; thrives in a fast‑moving, ambiguous environment.

THE ROLE

We are seeking highly skilled and motivated Senior/Staff Digital Design Engineers with a strong focus on CMOS digital design to take end‑to‑end ownership of high‑speed, real‑time data‑processing silicon—from early algorithm modelling to verified RTL and silicon bring‑up. You will join a multidisciplinary group creating next‑generation OTPUs where digital, optical and mixed‑signal domains intersect. The ideal candidate will have a strong background in electrical engineering and semiconductor physics, along with a passion for developing reliable, high-performance digital circuits that drive breakthrough AI hardware.

RESPONSIBILITIES

• Architect, design and implement high‑throughput digital pipelines (multi‑GSPS input rate, continuous streaming data paths, deep pipelining and hand‑shaking) in advanced CMOS nodes.
• Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring‑up real‑time demos, exercise high‑speed transceivers, and feed learnings back into the ASIC.
• Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate‑level sign‑off.
• Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static‑timing closure, formal and constrained‑random verification.
• Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth‑per‑watt targets.
• Collaborate with optical‑hardware, mixed‑signal and software teams to optimise data‑converter interfaces, clock‑domain crossings and firmware abstractions.
• Mentor junior engineers, lead design reviews and champion best‑practice design methodologies.