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Job Description:

This position is responsible for, but not limited to, the following job duties:

• Work as part of a physical design team implementing chips from netlist to GDSii with good understanding of the technology elements as well as design flow in all stages.
• Responsible for floorplanning, design partition and block pin assignment.
• Perform blocks PnR, timing closure, physical verification.
• Perform blocks IR/EM analysis. Experience with chip level IR/EM analysis is a big plus.
• Familiar with scripting languages such as tcl, perl and python. Write scripts to automate physical design flow and make it more efficient.
• Expertise on low power IC design is desirable.
• Good knowledge on physical verification using Mentor’s Calibre tool.

Minimum requirements: Bachelor’s degree and 8+ years of related experience or Master’s degree with 5+ years of experience.
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $107,000 - $171,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence

• Work as part of a physical design team implementing chips from netlist to GDSii with good understanding of the technology elements as well as design flow in all stages.
• Responsible for floorplanning, design partition and block pin assignment.
• Perform blocks PnR, timing closure, physical verification.
• Perform blocks IR/EM analysis. Experience with chip level IR/EM analysis is a big plus.
• Familiar with scripting languages such as tcl, perl and python. Write scripts to automate physical design flow and make it more efficient.
• Expertise on low power IC design is desirable.
• Good knowledge on physical verification using Mentor’s Calibre tool