REQUIREMENTS:

• Excellent at scripts, C++/UVM OOP languages
• Experience in Verilog and System Verilog languages
• Strong understanding of computer architecture and ASIC design flow
• Experience with bus protocols (AXI, AHB, other)
• Build C/C++/UVM model for simulation
• Build test bench and monitors for DUT
• Compose test plan and validation vectors to ensure functional completeness
• Debug function/performance bugs of graphics, APU and server chips
• Prefer 3 or more years of experience in the ASIC design and verification industry
• Familiar with Linux Environment (including shell scripting and Linux GNU tools)
• Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
• Should be versatile in any one of the high-level verification flows such as SV, UVM, C++, etc., as well as knowledge of industry standard tools for verification
• Should have excellent communication skills (both written and oral)
• Strong problem-solving skills

EDUCATION:

• Major in EE, CS or related, Master’s Degree with 3+ years or a Bachelor’s degree with 5+ years of professional experience.
  

  LI-JR2

Requisition Number: 75819
Country: Canada State: Ontario City: Markham

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

RESPONSIBILITIES:

• Work with global Front-End System Management Unit design team for verification of large scale ASIC microprocessor, network-on-chip, security, and SOC clock and reset functions.
• Develop and implement C-based directed tests and SystemVerilog UVM constrained random test sequences.
• Improve existing UVM test bench with advanced design verification methodology.
• Work on power-aware flow and bring up NLP for Power Gating simulation.
• Develop and execute verification test plans and testbench component plans and drive reviews with peers and stakeholders.
• Develop testbench components including stimulus drivers, monitors and checkers.
• Develop, simulate and debug directed and random stimulus and assembly level tests.
• Develop and analyze assertions and coverage terms. Participate in technical reviews of the specifications, design and test plans. Identify and address areas of concern to meet design quality objectives.
• Develop tools, infrastructure, processes and flows to enable functional verification.
• Maintain and improve existing functional verification infrastructure and methodology.
• Independently develop quality, timely and cost-effective solutions.