SKILLS & EXPERIENCE

• 12 + years in analog or mixed‑signal IC design with at least 3 complete tape‑out cycles as Senior IC / Lead on products operating > 10 GHz and achieving < 1 ns end‑to‑end settling time.
• Demonstrated success leading teams that delivered multi‑block analog front ends—ADCs/DACs, TIAs, SerDes, PLL/CDR—into high‑volume production on advanced CMOS nodes.
• Deep expertise in low‑latency sampling circuits, broadband feedback networks, ultra‑low‑jitter clocking, package / PCB co‑design, and parasitic‑aware layout sign‑off.
• Solid understanding of mixed‑signal interaction collaborating with the digital lead and agreeing specification splits.
• Strong preference for AI‑compute silicon experience—analog accelerators for activation functions, non‑linear transforms, layer‑norm or in‑memory compute—with quantified power‑latency achievements.
• Mastery of the standard tool chain: Cadence Virtuoso & SpectreRF, EM extraction (EMX/HFSS), mixed‑signal verification (AMS Designer, Questa ADMS), and production test correlation.
• Prior people‑management responsibility: hiring, mentoring, salary planning and performance management for engineers.
• Excellent project‑leadership skills: schedule ownership, risk analysis, vendor/foundry engagement, first‑pass success mindset.
• Outstanding written and verbal communication; comfortable presenting detailed technical and program status to executives, customers and cross‑site teams.

THE ROLE

We’re searching for a ASIC Lead (Analog) to direct the conception‑to‑production development of Flux’s analog ASICs with multiple high‑speed analog subsystems—20 GSPS data converters, TIAs, ultra‑low‑jitter PLLs, and 100‑lane SerDes fabrics—all with end‑to‑end signal paths that settle in < 1 ns.
This is a hands‑on leadership position: you will manage and mentor a multidisciplinary team, own program execution to tape‑out, and serve as the principal technical authority for every analog block that underpins our OTPU.

RESPONSIBILITIES

• Architect and drive full ASIC analog strategy—converter front ends, clocking, optical IO, power regulation and on‑chip non‑linear compute engines—ensuring bandwidth, latency, noise and power budgets are simultaneously met.
• Lead and line‑manage 6 - 12 analog IC and physical‑layout engineers: goal‑setting, performance reviews, recruiting, and skills development and maintain a culture of rapid, first‑time‑right design.
• Collaborate with digital leads to guarantee end-to-end timing determinism and low-latency control loops.
• Implement agile, milestone‑driven schedules that hit aggressive tape‑out dates; track risk burn‑down and drive cross‑function resolution with digital, photonics, packaging and firmware groups.
• Champion rigorous design‑review and verification processes (block and top‑level), including behavioural modelling, corner / Monte‑Carlo sign‑off, and lab‑to‑simulation correlation.
• Represent analog interests in executive and customer/partner communications; create concise technical roadmaps, risk assessments and silicon performance updates.