Verification Engineer – Digital ASIC / System on Chip (SoC) Design

at  FraunhoferInstitut fr Integrierte Schaltungen IIS

The Fraunhofer-Gesellschaft (www.fraunhofer.com) currently operates 76 institutes and research institutions throughout Germany and is the world’s leading applied research organization. Around 30 000 employees work with an annual research budget of 2.9 billion euros.

APPLY ONLINE NOW (MOTIVATION LETTER, CV, CERTIFICATES). WE LOOK FORWARD TO GETTING TO KNOW YOU!

Questions about this position will be answered by Simon Zimmermann.
Fraunhofer Institute for Integrated Circuits IIS
www.iis.fraunhofer.d

• By performing feature extraction from register-transfer level (RTL) specifications, you will produce verification plans that are supported by metrics obtained from simulation.
• You will also generate, maintain, and expand test benches based on the UVM framework.
• Using your profound knowledge, you will also contribute to tasks like test development and debugging.
• When working with a device under test (DUT), you will develop precise coverage models.
• By writing SVA assertions and scoreboard checkers, you will ensure the correct operation of the DUT.
• Last but not least, you will prepare, execute and analyze regression runs