ABOUT THE JOB YOU’RE CONSIDERING

Join a collaborative and innovative team as an RTL Design Engineer, where you’ll contribute to cutting-edge ASIC development in a dynamic, multi-disciplinary environment. In this role, you’ll design and maintain synthesizable RTL for SoC and subsystem components, working closely with architecture, verification, and physical design teams across global sites. You’ll help ensure performance, power, and quality goals are met through simulation, debugging, and integration support, while contributing to technical discussions and emulation efforts.

YOUR SKILLS AND EXPERIENCE

• Bachelor’s or Master’s degree in Electrical or Computer Engineering, with 5+ years of hands-on RTL design experience targeting advanced ASIC technologies.
• Proficiency with ASIC design tools (Synopsys, Cadence), including lint, CDC, LEC, and gate-level simulations.
• Strong scripting skills (Python, Perl, TCL, Bash) for automation and efficiency.
• Solid understanding of SoC integration, bus protocols (AXI, AHB, AMBA), and networking/encryption standards.
  Life at Capgemini

Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:

• Flexible work
• Healthcare including dental, vision, mental health, and well-being programs
• Financial well-being programs such as 401(k) and Employee Share Ownership Plan
• Paid time off and paid holidays
• Paid parental leave
• Family building benefits like adoption assistance, surrogacy, and cryopreservation
• Social well-being benefits like subsidized back-up child/elder care and tutoring
• Mentoring, coaching and learning programs
• Employee Resource Groups
• Disaster Relief

About Capgemini
Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem. The Group reported 2024 global revenues of €22.1 billion.
Get the future you want | www.capgemini.com
Disclaimer
Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship.
Capgemini is committed to providing reasonable accommodations during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.
Please be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process.
Applicants for employment in the US must have valid work authorization that does not now and/or will not in the future require sponsorship of a visa for employment authorization in the US by Capgemini.
Job Developer
Schedule Full-time
Primary Location CA-ON-Markham
Organization ERD PPL CA

• Design and maintain RTL for SoC and subsystem components using Verilog/SystemVerilog
• Collaborate with architecture, design, and verification teams across multiple time zones
• Support synthesis, timing closure, and power optimization efforts
• Debug simulation failures and assist in post-silicon validation
• Contribute to emulation activities and technical status meetings