SKILLS & EXPERIENCE

• 7 + years of production CMOS data‑converter design, with at least two tape‑outs running 20 GHz analog bandwidth.
• Deep knowledge of track‑and‑hold linearity, aperture‑jitter minimisation, current‑steering DAC glitch energy reduction, capacitor and device matching, and metastability‑hard comparators.
• Proficiency with industry EDA flows: Cadence Virtuoso, SpectreRF / AFS RF, Verilog‑A/AMS, EMX / HFSS for package + on‑chip inductor modelling, and mixed‑signal verification.
• Demonstrated ability to achieve < 100 fs rms aperture jitter, < 0.5 LSB DNL/INL (post‑calibration), and low‑ppm clock‑to‑data skew in silicon.
• Experience incorporating digital calibration engines (DSP or µ‑controller‑driven) for offset, gain, timing and element‑mismatch correction.
• Solid grasp of supply‑noise coupling, substrate isolation, ESD, latch‑up, and advanced‑node layout techniques (double patterning, EUV constraints, local interconnect).
• Strong lab skills: high‑speed AWG/BERT operation, FFT‑based dynamic testing, de‑embedding, and scripting (Python / MATLAB) for data reduction.
• Bachelor’s degree in Electrical Engineering or related field (Master’s / PhD preferred).
• Excellent communication, cross‑disciplinary collaboration, and a demonstrated ability to execute quickly in innovation‑driven environments.

THE ROLE

We’re searching for a Senior/Staff Analog Design Engineer to architect, design and bring to production ultra‑high‑speed (> 20 GHz analog bandwidth, > 40 GS/s) CMOS ADCs and DACs that directly interface with our optical compute fabric.
Success in this role requires mastery of low‑jitter sampling circuits, broadband front ends, and calibration techniques that deliver outstanding ENOB and power efficiency. The ideal candidate will have a strong background in electrical engineering and semiconductor physics, along with a passion for developing reliable, high-performance analogue circuits that drive breakthrough AI hardware.

RESPONSIBILITIES

• Define converter architectures that will deliver on the target of Analog bandwidth > 20 GHz.
• Design critical high‑speed building blocks: bootstrapped or switch‑linearised T/H, low‑skew clock trees (< 50 fs rms aperture jitter), broadband input buffers, thermometer and binary‑weighted current cells, dynamic element matching (DEM) and background calibration loops.
• Model and close performance using transistor‑level and behavioural co‑simulation (SpectreRF / AFS RF + Verilog‑A/AMS), then drive post‑layout extraction, EM/IR and thermal analysis to achieve first‑silicon success.
• Collaborate with packaging, SerDes and PLL teams to co‑design I/O impedance, ESD, supply isolation and on‑interposer routing so converters integrate cleanly into multi‑lane fabrics.
• Lead silicon bring‑up: on‑wafer static and dynamic tests, high‑speed digitiser / AWG measurements, DNL/INL, static‑power and jitter transfer characterisation; oversee production test pattern generation and built‑in self‑test (BIST) hooks.
• Mentor junior engineers, conduct rigorous design and layout reviews, and publish internal app‑notes to disseminate best practices for GHz‑class data‑converter design.
• Track and inject into the team the latest advances in time‑interleaving calibration, background mismatch correction, supply‑noise tolerant reference generation and layout techniques.