JOB DESCRIPTION

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world’s most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany.
As part of Intel’s strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in High-Volume Manufacturing (HVM) at a 2-year cadence going forward.
Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.
This job requisition is to seek Data Science (DS) team engineering roles in FSM HVM Global Yield organization, reporting to Data Science team manager. Selected candidates will work with other members in Global Yield org including Process Integration, Device and Defect engineering teams, fab module/yield teams and TD team members to achieve yield ramp-up and process optimization in early production stage, supporting internal and external customers.

QUALIFICATIONS

You must possess the minimum qualifications below to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. The experience listed below may be obtained through schoolwork, classes and project work, internships, military training, and/or work experience.

MINIMUM QUALIFICATIONS:

• Masters or PhD degree in Computer Science, Physics, Chemical Engineering, Electrical Engineering
• Experience in python or other program languages to develop analysis. method and algorithms using large amount of data

PREFERRED QUALIFICATIONS:

6+ months of experience in one of the following:

• Experience in big data analysis and machine learning.
• Experience in advanced node semiconductor high-volume manufacturing.
• Experience with Device Physics and overall FinFET process flow.
• Statistics Coursework, Statistical Process Control (SPC) or Design of Experiments (DOE) principles, and engineering analysis tools.
• Experimental lab work.
• Semiconductor and transistor device physics.
• Data analysis skills with demonstrated ability to construct clear data-based problem statements.

• Provides process development direction throughout the whole lifecycle of a technology node by identifying root cause yield limiters.
• Performs statistical analysis, develops visualizations and presentations to construct accurate process development roadmaps that drive technology yield milestones.
• Develops methods, processes, and systems to consolidate and analyze diverse big data sources, establishing optimal methodologies for defect-mode understanding and yield modeling, leading to accurate yield Pareto construction and process roadmap definition.
• Organizes, interprets, and structures insights from fab process, defect, and electrical data and detects data anomalies and drives process changes for yield enhancement.
• Extracts insights from structured and unstructured data by quickly synthesizing large volumes of data, and applying statistics, machine learning and coding techniques.
• Develops systems to transform complex experimental and manufacturing data into yield improvement actions using knowledge of product design and test features.
• Ensures manufacturability over process and product design through thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp.
• Executes new product introductions, enables design-technology co-optimization, and participates in design of experiments in factory task forces.
• Creates cross-functional collaborations across organizations to debug yield limiters in design, test, and process development areas.
• Develops tools, multivariate algorithms, and methodologies to perform high-volume data analysis to identify root cause yield limiters and identify key process changes to advance yield improvement.
• Performs fault isolation and failure analysis to determine the root cause of failures by evaluating the electrical characteristics of the components using various tools and techniques such as ATE testing, DFx software tools, optical probing, logic/circuit simulation, and emulation, probing, and layout study.
• Develops measurement recipes to provide quick and accurate feedback on product integrity, helping resolve issues with yield or product quality impact.
• Develops and hardens equipment capable of meeting operational and capability needs for leading edge logic node.
  Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.
  See https://www.intel.com/content/www/us/en/jobs/benefits.html for more details.
  

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