Analog Design Engineer - Phase Lock Loop

at  AMD

Job Description

PREFERRED EXPERIENCE:

Strong experience in the semiconductor industry
Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm
Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.
Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.
Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis. Helic/EMX is a plus.
Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)
Proficiency in scripting languages like Perl, Python, matlab etc. is a plus.
Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy
Possess strong analytical/problem solving skills and pronounced attention to details
Must be a self-starter, and able to independently drive tasks to completion

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_

THE ROLE:

AMD is searching for an experienced Circuit Design Engineer to join the fast-growing PLL design team, responsible for defining, specifying, and implementing current and future advanced PLL IPs powering AMD products.
Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! Looking forward to welcoming you in the team!

KEY RESPONSIBILITIES:

Design of complex building blocks of LC PLL and RO PLL including architecture development and transistor level circuit design
Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
Work closely with mask design engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution
Lead/mentor junior engineers