Analog Design, Sr Manager

at  Synopsys

WE ARE LOOKING FOR SENIOR R&D MANAGER TO JOIN OUR TEAM AND LEAD THE HIGH-PERFORMANCE SERDES IP DESIGN.

In this role, you will guide a team working on the design, development, and refinement of PAM4 SERDES IP. . You will be part of a fast-growing analog and mixed signal R&D team developing high speed analog integrated circuits in the latest FinFET CMOS processes. We are looking for an engineer with theoretical knowledge and practical experience to contribute to the team. Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You will work with a cross functional design team of analog, digital and top level integration designers from a wide variety of backgrounds. Our design environment is best-in-class with a full suite of IC design tools, supplemented by custom in-house tools, and supported by an experienced software/CAD team.

Job Responsibilities

• Manage and mentor the activities of a team of senior engineers focused on high-speed SERDES IP development across multiple projects
• Define architecture specifications and circuit implementation requirements for next-generation SERDES PHY IPs
• Ensure adherence to project schedules, quality metrics, power/area targets through effective team oversight
• Identify and refine circuit architectures to achieve optimal power, area and performance targets.
• Collaborate with cross-functional teams (digital design, physical design, CAD) to integrate analog IP components
• Partner with process engineering teams to enable robust analog IP across advanced FinFET nodes
• Continuously drive design methodology improvements and adoption of latest EDA tools/flows
• Hire, develop and retain top analog engineering talent through active mentorship

Key Qualifications

• MSc with 8+ years experience of IC design with a strong background in SerDes architectures
• 2+ years of people management experience leading high-performance analog design teams
• Familiarity with transistor level circuit design and CMOS design fundamentals
• Proven expertise in high-speed I/O design, architectures, circuits, and layout implementation
• Extensive knowledge of CDR, DFE, CTLE, EQ, decision feedback equalizer design techniques
• Hands-on experience with analog/mixed-signal design flows, tools, modeling
• Understanding of FinFET transistor characteristics and design challenges at advanced nodes
• Strong project management skills with the ability to manage multiple priorities
• Excellent communication and people leadership abilities to motivate cross-functional teams
• Good communication and documentation skills

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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Should you require an accommodation, please contact hr-help-canada@synopsys.com

• Manage and mentor the activities of a team of senior engineers focused on high-speed SERDES IP development across multiple projects
• Define architecture specifications and circuit implementation requirements for next-generation SERDES PHY IPs
• Ensure adherence to project schedules, quality metrics, power/area targets through effective team oversight
• Identify and refine circuit architectures to achieve optimal power, area and performance targets.
• Collaborate with cross-functional teams (digital design, physical design, CAD) to integrate analog IP components
• Partner with process engineering teams to enable robust analog IP across advanced FinFET nodes
• Continuously drive design methodology improvements and adoption of latest EDA tools/flows
• Hire, develop and retain top analog engineering talent through active mentorshi