Analog Design, Staff Engineer

at  Synopsys

Synopsys is the leading provider of high-quality, silicon-proven IP SerDes products, implemented on the most advanced CMOS technologies. We are looking for Analog Design Engineers to develop Synopsys’ highest speed SerDes products, supporting Ethernet and PCIe standards.
You will be part of a fast growing analog and mixed signal R&D team, developing high-speed analog integrated circuits in the most advanced FinFET/GAA process nodes.
You’ll interact with a global, dynamic, multi-cultural and cross-functional design team.

KEY QUALIFICATIONS

• M.Sc. degree on Electrical Engineering with 3+ years of experience or Ph.D. in Electrical Engineering
• Good team player
• Good analysis, problem-solving and organization skills
• Good written and verbal communication in English
• Familiarity with one or more IC design packages
• Familiarity with UNIX operating Systems

PREFERRED EXPERIENCE

• Previous industry experience on CMOS analog design or specialization (e.g. Ph.D.) in a relevant area (ADC, DAC, PLL, Rx, Tx, References, etc.) is preferred
• System level knowledge of SerDes system is a plus, but not mandatory

ABOUT US

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you

• Drive the design of analog circuits and guide junior engineers
• Develop and/or validate analog circuits considering electrical specifications and reliability constraints
• Document simulation results and prepare design reviews
• Define and plan of analog design activities and associated milestones.
• Evaluate the impact of parasitic effects related to layout implementations. Work with the layout team to minimize such effects, improving performance, power and area.
• Silicon correlation with simulation results