Analog/mixed-signal IC Modeling Engineer - Acacia
at Cisco Systems
Ottawa, ON, Canada -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 07 Nov, 2024 | Not Specified | 08 Aug, 2024 | 3 year(s) or above | C++,Publications,C,Ffe,Communications,Virtuoso,Cadence,Python | No | No |
Required Visa Status:
Citizen | GC |
US Citizen | Student Visa |
H1B | CPT |
OPT | H4 Spouse of H1B |
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Employment Type:
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Permanent | Independent - 1099 |
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Contract to Hire – Corp 2 Corp |
Description:
Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks.
MINIMUM REQUIREMENTS:
BSEE degree with 8+ years of experience, or equivalent, an MS degree with 6+ years of experience, or equivalent, or a PhD with 3+ years of experience, or equivalent.
Behaviour and IBIS-AMI modeling of high-speed IC in most of the areas below:
- High Speed Serial Links utilizing serializers, deserializers, and data convertors.
- High Performance Output Drivers
- High Performance Phase Locked Loops
- Phase interpolators
- Programmable Gain Amplifiers
- Equalization techniques (CTLE, FFE, DFE)
- Clock and Data Recovery
- Jitter analysis and attenuation techniques
PREFERRED REQUIREMENTS:
- Direct experience with electrical transceiver applications including backplane, optical, and cable communications
- Direct experience and familiarity of IEEE 802.3 and CEI standards using multiple modulation schemes
- Direct experience in signal integrity analysis.
- Proven track record of innovation
- Publications
SOFTWARE EXPERIENCE:
- C/C++
- Advance Design System (ADS)
- Matlab/Simulink
- Cadence (virtuoso)
- Spectre/APS/SpectreX
- Mixed signal simulations in AMS
- Python
Responsibilities:
As a member of the Mixed Signal Design team, you will be a key member of a small, dynamic IC Design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. You will assist in the architecture of behavioral models and IBIS-AMI models of interfaces to productize ultra-deep sub-micron-based CMOS products.
You will lead efforts to develop behaviour models and complex IBIS-AMI models of the analog IO development. This will require you to collaborate with packaging and hardware design teams to ensure models accurately represent the device performance. You will also assist applications engineering in model supports.
REQUIREMENT SUMMARY
Min:3.0Max:8.0 year(s)
Marketing/Advertising/Sales
Sales / BD
Sales
Graduate
Proficient
1
Ottawa, ON, Canada