Applications Engineering, Sr Staff Engineer
at Synopsys
Singapore, Southeast, Singapore -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 16 Oct, 2024 | Not Specified | 17 Jul, 2024 | 5 year(s) or above | Functional Verification,Critical Thinking,Rtl Design,Chipscope,Account Planning,Logic Analyzer,Validation,Completion,Assertions,Axi,Communication Skills,Upf,Rtl Coding,Product Training,Embedded Software,Debugging,Amba | No | No |
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US Citizen | Student Visa |
H1B | CPT |
OPT | H4 Spouse of H1B |
GC Green Card |
Employment Type:
Full Time | Part Time |
Permanent | Independent - 1099 |
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Description:
JOB DESCRIPTION AND REQUIREMENTS
Job Description:
Location: Singapore
Position: Applications Engineer, Sr Staff
The primary focus of Applications Engineer is to support the sale and deployment of Synopsys Emulation & Prototyping solution - including functional verification & validation, debugging, FPGA synthesis & partitioning, and embedded software bring-up on emulation/prototyping system. The candidate is expected to work directly with customers & Synopsys R&D to deliver technical solutions, product demonstrations, resolve technical issues and conduct product training. This will include pre-sales consultation and working with customer to validate their SoC design with Synopsys Emulation & Prototyping solution. He/She will also participate in account planning and work with the sales team to develop account strategy to grow Synopsys Emulation & Prototyping solution.
We are looking for a self-motivated and dependable individual with following technical skills:
- Strong knowledge and experience on design validation with Emulation or FPGA prototyping system from RTL design and experience in compiling/ design bring-up on a FPGA emulation/prototyping platform. SoC /architectural design with RTL coding or design verification using Xilinx/Altera FPGA.
- Knowledge on Xilinx Virtex 7/UltraScale Architecture and hands-on experience on ISE/Vivado Design Suite/Place & Route.
- Experience in Synopsys Emulation or Prototyping Solution will be an added advantage.
- Proficiency in Verilog/VHDL/SystemVerilog programming or scripting language.
- Knowledge on Simulation/VCS, Assertions (SVA) Coverage, Low Power verification with UPF is a plus.
- Good knowledge in Simulation flows, Assertion, DPI and transactors/ transaction-based verification.
- Sharp debugging and problem-solving skills on FPGA designs, hardware system and RTL design is desirable.
- Good understanding of SW/HW debug methodologies with prior experience in any of standard SW/HW debug tools (Identify, ChipScope, SignalTap, Logic Analyzer etc.)
- Experience in SoC bus/high speed protocols including following but not limited to AMBA, AXI, USB PCIE will be an advantage.
- Good critical thinking and problem-solving skills. Experience in project execution from start to completion.
- Pleasant personality with good interpersonal and communication skills.
- Some travel within Southeast Asia region up to 2 weeks per trip and occasional travel to USA are expected
- BS in CS/EE with 7-8 years of experience, or MS in CS/EE with 5-7 years of experience.
Responsibilities:
Please refer the Job description for details
REQUIREMENT SUMMARY
Min:5.0Max:8.0 year(s)
Information Technology/IT
Engineering Design / R&D
Software Engineering
BSc
Proficient
1
Singapore, Singapore