ASIC Design Engineer - Neural Engine DMA

at  Apple

SUMMARY

Posted: Jan 2, 2025
Role Number:200549158
Do you love crafting elegant solutions to highly sophisticated challenges? As part of our Hardware Technologies group, you’ll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly transparent role, you will be at the center of the Pixel IP design effort to accelerate machine learning applications. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.

DESCRIPTION

As an ASIC Design Engineer in the Pixel IP DMA team, you will work closely with architecture, design, and verification teams to build dedication and low power DMA engines. Apply your knowledge of flow control, arbitration, cache design, compression, pipelining, sequencers, and other techniques to coordinate moving large amounts of data between the memory subsystem and the Apple Neural Engine Core (ANE). In this front-end design role, your tasks will include: - Coding high-quality RTL, with embedded assertions and cover points. - Writing detailed micro-architectural specifications. - Collaborating with multi-functional teams to explore solutions that improve performance while minimizing power and area. - Working closely with design verification and formal verification teams to debug and verify functionality and performance. - Working independently and handle deliverables to align with the project goals and support multi-functional engineering efforts.

MINIMUM QUALIFICATIONS

• Bachelor’s degree + 10 Years of Experience

PREFERRED QUALIFICATIONS

• Experience in SoC front-end ASIC RTL digital logic design using Verilog or System Verilog.
• Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs.
• Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, and logic equivalence checks.
• Tight-knit collaboration skills with excellent written and verbal communication skills.
• Strong understanding of flow control, arbitration, address translation, caching, on-chip interconnects, and performance analysis.
• Prefer previous experience designing dedication DMA engines, multimedia IPs (especially AI/ML applications), data storage, memory controllers, networking, image processing, interconnects, and/or low power design.
• Prefer familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB), and relevant scripting languages (Python, Perl, TCL).

Please refer the Job description for details