ASIC Digital Design Engineer

at  Synopsys

Lisboa, Área Metropolitana de Lisboa, Portugal -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate04 Dec, 2024Not Specified07 Sep, 20242 year(s) or abovePerl,Technical Documentation,Communication Skills,Python,Unix,Artificial Intelligence,Verilog,It,Scripting,C++,Synopsys Tools,Tcl,C,MatlabNoNo
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Description:

ASIC DIGITAL DESIGN ENGINEER

Synopsys, a world leader in the Semiconductor IP industry, is seeking a Mixed Signal Verification Engineer whose mandate is to:

  • Work in a Digital and Verification Development team contributing to the development and validation of complex digital mixed signals for high-speed interface IP
  • Understand the IP from a System level, Analog and Digital
  • Understand ASIC design Flow
  • Engage in verification activities under supervision of more experienced personnel, and to exercise judgment to determine appropriate actions to achieve the required specifications.
  • Assembling and implementing Subsystem RTL / constraints and DFT architecture for internal subsystems.
  • Has a good understanding of the implementation flows and methodologies for deep sub-micron designs
  • Prepare and present reports outlining the outcome of technical projects.
  • Has expertise in Verilog RTL coding, Lint/CDC/RDC can be a bonus
  • Build productive working relationships, with different teams, cross project
  • Participate in applicable product/project reviews

KEY QUALIFICATIONS

  • University master’s degree in electronic/Micro-electronics engineering
  • Knowledge of IC design flows
  • Digital design knowledge
  • Digital tools understanding
  • Willingness to learn new things.
  • Good team-player
  • Organizational skills are essential.
  • Good problem-solving skills
  • Digital signal processing essential
  • Digital Logic understanding
  • Good English communication skills

PREFERRED EXPERIENCE

  • 2+ years of relevant experience is highly preferred
  • Experience in producing high-quality technical documentation is desirable
  • Experience with analog tools, preferable Synopsys tools
  • Good understanding of analog design
  • Experience in Verilog/VHDL
  • Proficiency in at least on programming language such as Python, C, C++ and MATLAB
  • Understating of in System Verilog /VMM/UVMExposure to Unix, Perl and TCL scripting

  • At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things(IOT). These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Responsibilities:

Please refer the Job description for details


REQUIREMENT SUMMARY

Min:2.0Max:7.0 year(s)

Electrical/Electronic Manufacturing

Engineering Design / R&D

Information Technology

Graduate

Engineering

Proficient

1

Lisboa, Portugal