ASIC Digital Design, Sr Engineer

at  Synopsys

SECURITY DIGITAL DESIGN AND VERIFICATION ENGINEER

For the Security IP team in Porto, we are looking for a digital design and verification engineer who will work in state-of-the-art IP cores and subsystems to extend the Security IP business, in the markets of (HPC) High Performance Computing, (AI) Artificial Intelligence and Automotive. In this role you would:

• Architecture and design RTL in Verilog and System Verilog
• Architecture and design test environments for digital hardware Security IP cores and complex subsystems, in System Verilog and UVM
• Hardware verification of IP cores and subsystems with modern verification techniques like UVM or formal verification
• In cooperation with hardware and software security experts, perform functional and performance analysis of embedded hardware/software IP solutions
• Work in an international team setup

Key Qualifications

• RTL design expertise of hardware IP components
• ASIC verification skills (using System Verilog, UVM, Verilog)
• Ability to create test environments specifications
• MSc or PhD in Electrical Engineering or Computer Science
• 6 years of relevant experience
• Good knowledge about IC Design flows and excellent problem solving and debugging skills
• Strong communication (written and verbal) and interpersonal skills

• Architecture and design RTL in Verilog and System Verilog
• Architecture and design test environments for digital hardware Security IP cores and complex subsystems, in System Verilog and UVM
• Hardware verification of IP cores and subsystems with modern verification techniques like UVM or formal verification
• In cooperation with hardware and software security experts, perform functional and performance analysis of embedded hardware/software IP solutions
• Work in an international team setu