ASIC Digital Design, Sr Engineer

at  Synopsys

Seeking a highly motivated and innovative design engineer with background in high-speed protocols. Working as part of an experienced digital design and verification team. The position offers an excellent opportunity to work with experts on several fields. The candidate will be involved at specify, design and implement phases of state-of-the-art products.

REQUIRED SKILLS:

• 1-year of relevant IP design experience
• Desire to learn and explore new technologies
• Demonstrate good investigation and problem-solving skills
• Be familiar with IP design flow and good at RTL design
• Solid RTL debug capability
• Knowledge in HBM/DDR and interface technologies such as UCie, PCIe, USB is a plus
• Knowledge in FrontEnd and/or BackEnd synthesis is a plus
  At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
  Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk

• Study standard specifications published by JEDEC
• Define micro architecture at block level based on IP architecture
• Work on RTL design based on predefined coding style, SVA is included
• Clean RTL check violations in lint, CDC, DFT and synthesis
• Run block level test to speed up IP verification
• Work with verification to debug and fix RTL issues
• Check synthesis timing and improve RTL design if required