ASIC Digital Design, Staff Engineer

at  Synopsys

JOB DESCRIPTION AND REQUIREMENTS

At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Synopsys is seeking a talented engineer for digital design and verification role. Stimulating, challenging and rewarding work. Excellent work environment and career development opportunities. The successful candidate will work on product development of DisplayPort and HDMI digital Controllers. We develop best in class designs using the latest best practice in verification to ensure their quality and we need the right people to keep making this happening.
As a worldwide organization short term travel may be required.

Key Qualifications and Experience:

• Degree in electronic engineering or computer science
• Problem solving skills
• Good communication skills in English
• Willingness to learn
• Team player
• Understanding of IC design flows
• Relevant work in previous projects
• Knowledge of Verilog/VHDL
• Knowledge of System Verilog/UVM

Advantageous qualifications

• Exposure to Unix, Python and TCL scripting
• Knowledge of DisplayPort, HDMI or similar video & audio protocols

Responsibilities

• Define verification plans and build verification environments for IP level designs using System Verilog with UVM.
• Apply advanced verification techniques like constrained random generation, functional coverage, assertions and formal verification to achieve functional safety metrics (including ISO26262 compliance) for automotive applications
• Write test cases, checkers, and coverage that implement the verification test plan.
• Provide technical leadership to junior engineers and interns

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

• Define verification plans and build verification environments for IP level designs using System Verilog with UVM.
• Apply advanced verification techniques like constrained random generation, functional coverage, assertions and formal verification to achieve functional safety metrics (including ISO26262 compliance) for automotive applications
• Write test cases, checkers, and coverage that implement the verification test plan.
• Provide technical leadership to junior engineers and intern