ASIC Digital Verification Engineer

at  Synopsys

The selected candidate will be a technical leader of Synopsys DesignWare Processor team involving in development of leading edge DesignWare processor IP products such as HPC processors, NN accelerators, vision processors, as well as energy-efficient processors.
The responsibility is to take full ownership and accountability on quality of delivery for at least one or more blocks of verification functions within a product development effort. This may include but not limited to authorship of plans and specs for owned functions, guiding, coaching, and tracking others for appropriate execution with necessary technical works, as well as escalation of overall team competences.
The technical works could be applied to architecture, micro-architecture, performance analysis, logic design, verification and validation, as well as related engineering flows or environments and necessary signoff delivery processes.
Depending on individual’s capability and career development, the works may include but not limited to investigation, creation, implementation, analysis, debugging, and optimization in said areas. In addition, the candidate would have great opportunities to collaborate with cross-team or cross-site colleagues on various technical matters such as algorithms, methodologies, quality of delivery, SoC prototyping, system bring-up, or any other engineering works that are required for overall business operations.

KEY REQUIREMENTS:

• Master’s degree in EE or CS related engineering major is required as a minimum from a reputed college
• Minimum 10 years of experience in related digital frontend design or verification for IP business
• Proven leadership and ownership experience with solid quality of delivery and escalation of overall team capability.
• Comprehensive knowledge in microprocessor architecture, memory architecture, and system architecture
• In-depth hands-on experiences in architecture, micro-architecture and RTL design, or functional and performance modeling, performance profiling, performance benchmarking, or simulation verification based on UVM with co-simulation, functional formal, functional coverage, regression flows/environments and respective debugging activities, plus authorship of technical specs
• Programming skills: SystemVerilog, SystemVerilog Assertion, Verilog, C/C++, assembly, Perl, Python, scripts
• Tools: RTL linters, simulators, synthesizers, functional formal, functional coverage, teamwork tools (continuous integration, source control management, issue tracking, etc.), ADL-based generation tools (such as Synopsys ASIP Designer), or software toolchains
• Experience with multi-site development is essential
• Project management skills: requirement profiling, resource, work, and schedule planning and tracking, risk and quality assessment and management, as well as justification on execution objective, strategy, value proposition, and ROI evaluation
• Written and Verbal communication skills in English
• Creation, modification and review of documentation: design or verification work plans, engineering quality processes, test scenarios, test reports
• Ability to profile the values, requirements, issues, risks, and solutions for engineering works presentation and persuade and compromise for consensus
• Ability to follow disciplines describing issues and changes in track systems

ANALYTICAL SKILLS:

• Analysis of signoff requirements for product releases
• Ability to analyze QoR and verification results for major milestone reviews and assessments.
• Self-motivated team player with leadership, be able to thrive in a fast-paced engineering environment
• Ability to guide, coach, motivate, and influence team members toward desired results

Please refer the Job description for details