ASIC Digital Verification, Staff Engineer

at  Synopsys

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

• Seeking a highly motivated and innovative ASIC digital verification engineer with relevant experiences.
• Working as part of a highly experienced mixed-signal design team, the candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB SERDES products.
• The position offers an excellent opportunity to work with an expert team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs from creating test plans to performing functional and performance tests on the test-chips/products

SKILLS REQUIRED:

• BS/MS in Electrical, Electronics or related fields with 5+ years of industry experience with digital verification methodology such as VMM/UVM
• Good experience in writing testcases in Verilog and System Verilog
• Good experience in debugging complex testbench and design related issues
• Good understanding of digital circuit design
• Basic understanding of C/C++ and RISC processors
• Familiarity with scripting languages (Python or Perl)
• Self-learner/independent, good organization and communication skills for interacting with teammates

• System Verilog Assertions / formal verification
• Creating and updating test plans and test cases
• Writing modular constrained-random/coverage driven Verilog, SystemVerilog and UVM/VMM testbenches
• Writing SystemVerilog assertions
• High-speed digital & mixed-signal design work
• Monitoring simulation regressions and debugging RTL and Gate level simulation failures
• Writing functional coverage and performing functional/code/assertion coverage analysis
• Tracking/Reporting issues in Jira and documenting in Confluence