ASIC Digital Verification, Staff Engineer

at  Synopsys

AT SYNOPSYS, WE’RE AT THE HEART OF THE INNOVATIONS THAT CHANGE THE WAY WE WORK AND PLAY. SELF-DRIVING CARS. ARTIFICIAL INTELLIGENCE. THE CLOUD. 5G. THE INTERNET OF THINGS. THESE BREAKTHROUGHS ARE USHERING IN THE ERA OF SMART EVERYTHING. AND WE’RE POWERING IT ALL WITH THE WORLD’S MOST ADVANCED TECHNOLOGIES FOR CHIP DESIGN AND SOFTWARE SECURITY. IF YOU SHARE OUR PASSION FOR INNOVATION, WE WANT TO MEET YOU.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

KEY QUALIFICATIONS:

• Candidate should have a proven desire to learn and explore new technologies.
• Demonstrates good communication skills in English.
• Demonstrates good analysis and problem-solving skills.
• Prior knowledge CAD tool for development.
• Working experience with Verilog and SystemVerilog.
• Working experience with scripting languages.

PREFERRED EXPERIENCE:

• Understanding of high speed interface protocols such as HBM, DDR, DFI;
• Understanding of verification methodology such as UVM is a plus
• Typically requires no a minimum of 2 years of related work experience.

• Generates verification specifications.
• Develop test bench design and test cases.
• Evaluates and exercises various aspects of the development flow which may include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics.
• Generates documentation for testplans, verification environments, and usage.
• Participate in evaluation and troubleshooting of digital and mixed signal designs.